1. Field of the Invention
The invention relates to non-volatile memory such as flash memory.
2. Description of Related Art
Non-volatile memory such as flash memory is programmed by storing electrons. In the case of re-usable memory an erase step is involved prior to re-programming a memory cell. Two typical flash memory cells are shown in FIGS. 1 and 2. FIG. 1 is a stacked gate flash having a dual gate 10, one of the gates being a floating gate for storing electrons. A drain 14 and source 16 are formed in a well or substrate to define the transistor-like structure of the memory cell. FIG. 2 shows a structure 20 in which the gate 29 is separated from the well or substrate by a nitride layer for storing electrons. Again the memory cell includes a drain 24 and source 26.
One approach to programming the flash memory cell such as the cells of FIGS. 1 and 2 involves injecting electrons into the storage layer 12, 29 by Fordheim tunneling. In particular channel-hot-electron (CHE) programming techniques are used to impose an electron charge on the storage layer, in which a high gate voltage, e.g., 8-12 V is applied to the control gate 19 in FIG. 1 or the gate 29 in FIG. 2, while a lower voltage, e.g., 4-6V is applied to the drain 14, 24.
The erasing of the memory cells, in turn, involves the removal of electrons from the storage layer of the addition of holes. One technique is known as band-to-band induced hot hole (BBHH) injection in which a negative voltage, e.g., −3 to −8 V is applied to the control gate 19 or gate 29 while a positive voltage of 4 to 8V is applied to the drain 14, 24.
It will be appreciated that in both the program and the erase phases, a substantial amount of current is needed. This therefore limits the number of parallel memory cells that can be programmed in any one step.
A further problem arises from the fact that not all memory cells can be programmed by applying the same voltage across the gate and drain. Manufacturing variations will invariably cause substantial differences in the voltage required to program or erase the various memory cells in a non-volatile memory array. For example, it is normal to find that some cells in a memory array can be programmed at an applied drain voltage of as low as 3V. Others will not be programmed until a voltage of 6.5-7 V is applied. Therefore, in order to ensure proper programming and erasing of all memory cells the cell with weakest attributes, e.g. for programming purposes, the cell that requires the greatest drain voltage dictates the voltage that has to be generated. For example if a current of 300 μA is needed for each memory cell and the weakest cell requires a drain voltage of 6.5V to be effectively programmed, the charge pump for a 4-bit simultaneously programmed flash array needs to be capable of generating 1.2 mA at 6.5 V in order to deal with the worst case scenario. The programming voltage is also a function of the supply voltage Vcc and temperature, thus low Vcc and high temperature tend to require higher programming voltages.
Clearly, that process can be time consuming and cumbersome. The present invention seeks to provide a more efficient approach to programming and erasing non-volatile memory cells.